MAX19711ETN+T【PDF 22/36 页】IC ANLG FRNT END 56-TQFN

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Sheet目录2009

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MAX19711

10-Bit, 11Msps, Full-Duplex

Analog Front-End

______________________________________________________________________________________

Applications Information

Using Balun Transformer AC-Coupling

An RF transformer (Figure 10) provides an excellent

solution to convert a single-ended signal source to a

fully differential signal for optimum ADC performance.

Connecting the center tap of the transformer to COM

provides a VDD / 2 DC level shift to the input. A 1:1

transformer can be used, or a step-up transformer can

be selected to reduce the drive requirements. In gener-

al, the MAX19711 provides better SFDR and THD with

fully differential input signals than single-ended signals,

especially for high input frequencies. In differential

Figure 9. Aux-ADC Conversions Timing

CS/WAKE

2. CONTINUOUS AUX-ADC CONVERSIONS

tDCS

tCONV

SCLK

DIN

DOUT

D0 HELD

FIRST 10 BIT AUX-ADC

CONVERSION RESULT IS

SHIFTED OUT ON DOUT ON

THE FALLING EDGE OF SCLK

MSB FIRST

SECOND 10 BIT AUX-ADC

CONVERSION RESULT IS

SHIFTED OUT ON DOUT ON

THE FALLING EDGE OF SCLK

MSB FIRST

AD10 = 1, AD0 = 1,

PERFORM CONVERSION,

DOUT ENABLED

AD10 = 1, AD0 = 1,

PERFORM CONVERSION,

DOUT ENABLED

AD10 = 1, AD0 = 1,

PERFORM CONVERSION,

DOUT ENABLED

DOUT TRANSITIONS FROM

HIGH IMPEDANCE TO LOGIC-

HIGH INDICATING START OF

FIRST CONVERSION

DOUT TRANSITIONS HIGH

INDICATING START OF

SECOND CONVERSION

DOUT TRANSITIONS HIGH

INDICATING START OF

THIRD CONVERSION

DOUT TRANSITIONS LOW

INDICATING END OF FIRST

CONVERSION, DATA IS AVAILABLE

AND CAN BE SHIFTED OUT IF DOUT

IS ENABLED, AD0 CLEARED

DOUT TRANSITIONS LOW

INDICATING END OF SECOND

CONVERSION, DATA IS AVAILABLE

AND CAN BE SHIFTED OUT IF DOUT

IS ENABLED, AD0 CLEARED

DOUT TRANSITIONS LOW

INDICATING END OF THIRD

CONVERSION, DATA IS AVAILABLE

AND CAN BE SHIFTED OUT IF DOUT

IS ENABLED, AD0 CLEARED

AUX-ADC REGISTER

ADDRESS

tCSD

tCD

tCHZ

CS/WAKE

SCLK

1. SINGLE AUX-ADC CONVERSION WITH CONVERSION DATA READOUT AT A LATER TIME

DIN SET HIGH DURING SINGLE READ

D0 HELD

DIN

DOUT

AD10 = 0, AD0 = 1,

PERFORM CONVERSION,

DOUT DISABLED

DOUT TRANSITIONS FROM

HIGH IMPEDANCE TO LOGIC-

HIGH INDICATING START OF

CONVERSION

DOUT TRANSITIONS LOW

INDICATING END OF CONVERSION,

DATA IS AVAILABLE AND CAN BE

SHIFTED OUT IF DOUT IS ENABLED,

AD0 CLEARED

IF AUX-ADC CONVERSION

DOES NOT NEED TO BE

READ IMMEDIATELY, THE SPI

INTERFACE IS FREE AND

CAN BE USED FOR OTHER

FUNCTIONS, SUCH AS

HOUSEKEEPING AUX-DAC

ADJUSTMENT, ETC.

AUX-ADC REGISTER

ADDRESS

CONVERSION RESULT DATA

BIT D0 IS HELD FOR THE SIX

LEAST SIGNIFICANT BITS

DOUT TRANSITIONS TO

HIGH-IMPEDANCE

10 BIT AUX-ADC

CONVERSION RESULT IS

SHIFTED OUT ON DOUT ON

THE FALLING EDGE OF SCLK

MSB FIRST

AUX-ADC REGISTER

ADDRESS

AD10 = 1, AD0 = 0,

AUX-ADC IDLE

(NO CONVERSION),

DOUT ENABLED AND

CONVERSION DATA IS

SHIFTED OUT ON NEXT

CS/WAKE FALLING EDGE

FIRST FALLING EDGE OF

CS/WAKE AFTER DOUT IS

ENABLED STARTS SHIFTING THE

AUX-ADC CONVERSION DATA ON

THE FALLING EDGE OF SCLK

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